Engineering Recruitment Hub
Innovation at Speed and Scale
Everything you need to know about joining the team building the world’s first unified silicon architecture. One chip. One architecture. Your next career move.
Recruiter-Curated Resource for Engineering Candidates
Everything you need to know about joining the team building the world’s first unified silicon architecture. One chip. One architecture. Your next career move.
I've built these Gemini-powered agents to help you navigate your candidacy and understand our complex architecture.
Paste your summary or skills, and I'll have Gemini match you to the right Silicon One engineering team for our next chat.
Ask Gemini to explain any technical term from this page in simple terms.
Ready for Step 3? Let Gemini quiz you on high-performance C++ and networking fundamentals specifically for the Silicon One stack.
The networking industry was once defined by fragmented architectures. Cisco Silicon One fundamentally changed this, delivering the only unified networking silicon architecture that spans every role in the network.
A single architecture that scales from service provider core to enterprise campus. Source
Powering next-gen clusters with G200/P200 families (51.2 Tbps). Source
Exclusive partner silicon for NVIDIA’s Spectrum-X Ethernet platform. Source
"Erasing the false choice between Merchant and Custom silicon."
A100 (Enterprise Campus) & E100 (Smart Switches)
Scales from 3.2 Tbps to 51.2 Tbps with a single common SDK.
Modular architecture built from repeatable "Slices" (Receive NPU, Transmit NPU, Traffic Manager).
Scales up to 3 exabits (3-layer)
Native P4 processing avoids the "packet recycling" penalty. Future-proof support for emerging AI protocols without hardware upgrades.
Zero-Penalty Flexibility
The 'Write Once, Read Once' design ensures data never moves unnecessarily, maximizing burst performance for AI traffic surges.
100% Shared Buffering
Reduces job completion times (JCT) by up to 1.6x compared to generic Ethernet.
The Silicon One software organization is composed of specialized teams working across the entire stack.
Building the hardware interaction foundation, managing registers, and core initialization.
Developing sophisticated forwarding logic and high-performance packet classification.
Implementing the Switch Abstraction Interface for industry-standard network operating systems.
Crafting the P4-programmable toolchain that translates logic to high-speed silicon operations.
Optimizing system-wide data movement and protocol serialization for extreme throughput.
Traffic Management, Optical, Diagnostics
Core Programming
High-performance modern C++ for our SDK and SDK components.
Python & Automation
Testing frameworks, infrastructure scripts, and rapid prototyping.
Linux Environment
User-space and kernel-space development on x86 platforms.
Academic Background
B.Sc/M.Sc in Computer Science, Computer Engineering, or a related field.
Professional Experience
4+ years of professional or academic experience in Software Development.
Domain Expertise
3+ years in C++, Embedded Dev, or knowledge of ASIC/hardware processes.
Note: Specific requirements may vary by team and seniority level.
Submit your profile for our open SW Engineering positions.
30-minute deep-dive with me (your Reeeeeally Technical Recruiter)
2-hour session focused on coding, algorithms, and data structures.
2-hour technical deep-dive with our Team Leaders.
Join the team redefining the future of silicon.